1. Field of the Invention
The present invention relates to a parallel bit test (PBT) apparatus and PBT method and, more particularly, to a PBT apparatus and PBT method capable of reducing test time.
2. Description of the Related Art
In a semiconductor memory chip, a transmission error may occur while a data bit is transmitted after being encoded or while the data bit is outputted after being decoded. Alternatively, recorded data may be read wrongly due to a memory chip operation failure. Various test modes exist for checking a defective memory chip. A PBT apparatus and/or a PBT method uses one of various test modes.
A PBT mode is a test mode which can be used to test bit lines of a semiconductor memory chip, such as a dynamic random access memory (DRAM) chip, or the like. During a PBT, a write operation is performed on a DRAM chip in order to store data in each cell. Then, the stored data is read and tested by merging data loaded on data lines.
It is expensive and time consuming to test each cell or each bit line in order to check whether the data loaded on the bit lines is normal. Accordingly, the related art PBT apparatus uses a comparator formed of logic operation devices, such as an exclusive OR (XOR) gate, etc. Using the comparator, in effect, performs a data merge method which compresses the data loaded on data line. As described above, the PBT apparatus and/or PBT method is used to merge and parallel test the input data.
A related art multi-chip package (MCP) can have a structure in which a plurality of, e.g., four, identical memory chips are stacked. Each of the memory chips includes the same PBT apparatus therein. While performing a PBT, the four memory chips are sequentially tested one by one. That is, the four memory chips receive an input data signal via the same input line, and output an output data signal (or a representative data signal) via the same output line.
Since the four memory chips cannot simultaneously use the same output line, the four memory chips are sequentially parallel bit tested one by one. It takes a given amount of time t1 for testing one memory chip. Accordingly, when testing a MCP stacked with n memory chips, it takes a total amount of time t1×n.
In the four-chip example, when the memory chips receive 32 data signals DQ0 through DQ31 and output a representative data signal by comparing and determining whether the data signals DQ0 through DQ31 are the same, an output line of the representative data signal is DQ4. Here, a conventional PBT will receive n pieces of input data and will test the input data by merging them. Accordingly, less than n pieces of output data are outputted. A signal line can transmit one signal at a time due to bus accessibility. When a first one of the memory chips outputs the representative data signal DQ4 by performing a PBT for the given time t1 and the remaining three memory chips repeat the same PBT, it takes an amount of time t1×4 to test the four-chip MCP (again, an MCP stacked with four memory chips).
As described above, test time increases proportionally to the number of memory chips stacked in a MCP. That is, temporal efficiency decreases. Also, when test time increases, test cost also increases.